The current growth in the semiconductor industry has been driven by the aggressive scaling of the CMOS technology. In future CMOS technology generations, it is believed that supply and threshold voltages will continue to scale down to sustain performance demands, reduce switching power requirements and maintain device reliability. These continual scaling requirements of supply and threshold voltages combined with increasing integration density pose several technology and circuit design challenges. Since subthreshold leakage current increases exponentially with reduction in threshold voltage and temperature increase (due to increased device density), leakage power can become a major fraction of total power in the active mode. Therefore, there is a growing necessity to develop system-level techniques to counter this increment in leakage power.